1. Technical Field
The present invention relates generally to serial link data communications systems, and in particular, to clock and data recovery systems. Still more particularly, the present invention relates to a delay-locked loop circuit used to sample data based on a periodic clock signal.
2. Description of Related Art
In one common approach to serial data communications, clock information is not explicitly sent by a transmitter over the link, but is instead embedded in the data being transferred. In order to recover the data at the receiver, the clock signal must be extracted from this data stream. There are many approaches that may be used to solve this problem. One such approach is the use of a clock and data recovery phase-locked loop (PLL), in which the action of the loop adjusts the phase of an oscillator within the PLL to enable proper sampling of the incoming data. A second approach involves the use of a conventional delay-locked loop (DLL), offering smaller area, guaranteed stability, and better immunity against power supply noise. However, the use of conventional DLL circuits are limited in clock and data recovery (CDR) applications mainly because of the finite phase capture range of these types of circuits. A third approach to the clock and data recovery problem involves the use of a semidigital DLL. Compared to a conventional DLL circuit, a semidigital DLL circuit provides a phase shift by using a phase rotator under the control of a digital finite state machine (FSM). The use of a phase rotator in place of a finite-range delay line gives the semidigital DLL circuit an infinite phase capture range. This feature extends the usefulness of DLL circuits in CDR applications and even enables the circuit to track input data frequency drift to a certain degree. A semidigital DLL architecture offers advantages in multi-channel applications because a clock from a single voltage controlled oscillator (VCO) can be shared by multiple DLL circuits, saving clock generation area and mitigating crosstalk issues.
Turning to FIG. 1, a block diagram of a known semidigital DLL-based CDR using a phase rotator is shown. This prior art CDR includes DLL or PLL circuit 100, phase rotator 102, phase detector/sampler (PD/S) 104, and digital finite state machine (FSM) 106. DLL or PLL circuit 100 receives a clock reference signal, CLKref. The output of DLL or PLL circuit 100 is input into phase rotator 102. In turn, phase rotator 102 generates an output clock signal, CLKout at a frequency commensurate with that of CLKref and with a phase shift controlled by the action of the phase rotator. Phase detector/sampler 104 receives a digital data stream, DATin, and a clock signal, CLKout, used to generate information about the phase relationship between CLKout and DATin, and to sample DATin. Phase detector/sampler 104 also generates an output data stream, DATout. Phase detector/sampler 104 generates up (UP) or down (DN) signals in a digital data stream, which is received by digital finite state machine (FSM) 106. In turn, digital finite state machine 106 processes this information to produce appropriate control signals which are sent to phase rotator 102.
The operation of phase rotator 102 is based on the combination of phase selection and phase interpolation. Phase rotator 102 requires a multiphase input clock signal. In this circuit, output phases are generated by interpolating between weighted adjacent input phases. By choosing which phases have non-zero weights and by controlling the values of these weights, arbitrary phase shifting can be achieved. The multiphase clock signal may be generated in different ways, including being taken from an appropriate stage in a ring voltage controlled oscillator or by phase generation in the DLL from a single supplied phase.